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Packet Level Authentication (PLA): Performance

Current system

A proof of concept implementation based on Altera's Stratix II EP2S180 FPGA board is capable performing of 166,000 verifications per second with a 114 us latency per verification.

More details are available here.

Future possibilities

Converting design to a 90 nm structured ASIC using Altera's Hardcopy technology would increase performance to around 850,000 verifications per second while latency of a single operation would decrease to 89 us.

Performance can be increased further by converting the design to a more modern manufacturing process and by implementing a customized ASIC.

Power consumption estimation

According to Altera's simulation tools, an FPGA based PLA hardware accelerator design consumes about 120 uJ per packet verification. Converting the design to a structured ASIC would decrease power consumption to 30 uJ per verification. Using a more modern manufacturing process or customized ASIC would decrease power consumption further.

Thus, the power consumption of PLA related cryptographic operations is very low even for mobile devices. A standard 3.7 V/1000 mAh cell phone battery would have enough energy for verifying 444 million packets. With a packet size of 6000 bits per packet and 1 Mbps network connection, it would take one month of continuous usage to transmit such amount of data.

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Latest update: 30 April 2008.