Symbolic Model Checking of Hierarchical UML State Machines

Reference:

Jori Dubrovin and Tommi Junttila. Symbolic model checking of hierarchical UML state machines. In Jonathan Billington, Zhenhua Duan, and Maciej Koutny, editors, Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD'08), pages 108–117. IEEE Press, 2008.

Abstract:

A compact symbolic encoding is described for the transition relation of systems modeled with asynchronously executing, hierarchical UML state machines that communicate through message passing and attribute access. This enables the analysis of such systems by symbolic model checking techniques, such as BDD-based model checking and SAT-based bounded model checking. Message reception, completion events, and run-to-completion steps are handled in accordance with the UML specification. The size of the encoding for state machine control logic is linear in the size of the state machine even in the presence of composite states, orthogonal regions, and message deferring. The encoding is implemented for the NuSMV model checker, and preliminary experimental results are presented.

Keywords:

UML semantics, UML state machine, symbolic model checking, verification

Suggested BibTeX entry:

@inproceedings{DubJun:ACSD08,
    author = {Jori Dubrovin and Tommi Junttila},
    booktitle = {Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD'08)},
    editor = {Jonathan Billington and Zhenhua Duan and Maciej Koutny},
    pages = {108--117},
    publisher = {{IEEE} Press},
    title = {Symbolic Model Checking of Hierarchical {UML} State Machines},
    year = {2008},
}